Field Effect Transistor (FET) high frequency switches are well known in the field of signal transmission. High power high frequency (e.g., radio frequency (RF)) switches using transistor technology are extremely desirable due to their low DC power consumption as compared to traditional PIN diode switches.
FIG. 1a is a simplified diagram, partially in block and partially in schematic form, illustrating a prior-art single-pole double-throw (SPDT) high-frequency or radio-frequency switch 10. It is useful to note that the term “radio frequency” has a broad meaning, and encompasses essentially any frequency of alternating signal. In the past, the term “radio-frequency” related to the then-known frequencies which could be used to propagate radio waves, generally in the frequency range of a few kilohertz (KHz) to 1600 megahertz (MHz). Subsequent improvements in technology have made the upper limit of the term difficult to define, but the term may even include the frequencies of light waves. However, the meaning of RF does not include direct current (that is, signal having zero frequency). FIG. 1b illustrates a conventional mechanical switch symbol 8 the single-pole double-throw function of switch 10 of FIG. 1a. In FIG. 1b, a single movable “pole” 10M is hinged about an axis 11M for motion between two positions, the illustrated one of which causes throw 10M to be in contact with, and therefore make electrical connection to, independent, individual or separate “port” 62 and not to individual “port” 52, and the non-illustrated one of which results in connection of throw 10M to common “port” 52 and not to port 62. Thus, the single pole 10M can be set to one of two different “throw” positions, one of which connects common port 23 to individual port 52 and not to 62, and the other of which connects common port 23 to individual port 62, and not to 52.
In FIG. 1a, signal to be propagated is produced by a signal source designated generally as 12, which is illustrated as including a conventional voltage source 14 and series resistance or impedance 16. The signal produced by source 12 is intended to be selectively coupled to one of “load” resistances 20 and 22 by way of switch 10. Those skilled in the art know that the values of load resistances 20 and 22, and the internal resistance 16 of source 12, should match the characteristic or “surge” impedance of the transmission lines through which signals flow. The characteristic impedance of ordinary transmission lines as used for RF signal propagation ranges from about 50 ohms to about 300 ohms, but specialized transmission lines may have impedances as low as about ten ohms and higher than 300 ohms.
Signal from source 12 of FIG. 1a is applied by way of switch common node 23, a direct current (DC) blocking capacitor 18 and a node 24 to field-effect transistor (FET) arrangements designated as 30 and 40. FET arrangement 30 is illustrated as including a single FET 32, including source, drain and gate electrodes 32s, 32d, and 32g, respectively. Similarly, FET arrangement 40 is illustrated as including a single FET 42, including source, drain and gate electrodes 42s, 42d, and 42g, respectively. The symbol used to illustrate a FET, such as FET 32, is intended to include any type of FET, and specifically to include both enhancement- and depletion-mode FETs. The source terminal 32s of FET 32 is connected by way of a DC blocking capacitor 50 and an individual node 52 to load resistance 20. Similarly, source terminal 42s of FET 42 is connected by way of a DC blocking capacitor 60 and an individual node 62 to load resistance 22.
Those skilled in the art know that a field-effect transistor includes a controllable path or “channel” extending from the source electrode (source) to the drain electrode (drain), in which the voltage between the gate electrode (gate) and the conductive path or channel controls the conduction of the path or channel. FIG. 1c is a simplified conceptual representation of FET 32 of FIG. 1a. In FIG. 1c, the conductive “channel” of the FET is illustrated as an elongated region 70 extending from the source 32s to the drain 32d. The conduction of channel 70 is controlled by the electric field established between the conductive gate electrode 72 and the conductive channel 70. As mentioned, the conduction of the conductive channel extending between the source 32s and the drain 32d is controlled by the bias voltage applied between the gate 32g and the conductive channel 70. Since the channel 70 is conductive to a greater or lesser degree under many operating conditions, the control voltage may be applied between (in the electrical sense, rather than mechanical or positional sense, of the word “between”) the conductive gate structure 72 and either the source 32s or drain 32d. In FIG. 1a, the controllable conductive paths or channels of transistors 32 and 42 are designated 32p and 42p, respectively.
All conductors, and especially semiconductors, include inherent resistance. Thus, the conductive channel 70 of FIG. 1a may be represented by a resistance extending between the source 32s and the drain 32d. Such a resistance is illustrated as 70′ in FIG. 1d. The value of resistance 70 will depend upon the biasing of the gate-to-path or -channel region, being relatively small when the FET is ON or conductive, and relatively large when the FET is OFF or nonconductive. In this context, “small” and “large” are relative to the characteristic impedance of the transmission lines through which the RF signal flows, which is typically 50 or 75 ohms. Consequently, a path resistance of, say, 450 ohms in a 50-ohm system or 675 ohms in a 75-ohm system would be “large,” in that such a resistance would result in 20 decibels (dB) of attenuation, while a path resistance of, say, three (3) ohms in a 50-ohm system or 4½ ohms in a 75 ohm system would be “small,” in that the resulting attenuation would be about 0.5 dB.
In FIG. 1a, gate 32g of FET 32 is connected by way of a series resistance 92 to a node 93, and gate 42g of FET 42 is connected by way of a series resistance 94 to a node 95. Resistances 92 and 94 may be provided in the form of discrete resistors, or in any suitable other form. Generally, such resistors have a relatively large resistance, on the order of 1000 ohms or more, so as to limit gate current in the event of a momentary short-circuit or arc. However, such resistances are small by comparison with the input resistance or impedance of the gate electrode, and large by comparison with the characteristic impedance of the transmission lines of the system.
In FIG. 1a, a control voltage or bias voltage (bias) arrangement designated generally as 80 includes a source of direct voltage 82 illustrated by a battery symbol. Source 82 has a positive (+) terminal and a negative (−) terminal. The terminals of source 82 are coupled by way of a switch illustrated as a mechanical double-pole double-throw (DPDT) switch 84 to the gate terminals 32g and 42g of FETs 32 and 42. Those skilled in the art know that such mechanical representations are merely for the purpose of explanation, and that electronic switches are ordinarily used. The operation of DPDT switch 84 is straightforward, and merely has the effect of applying the positive voltage of source 82 to node 93 and the negative voltage to node 95 in one position of the switch, and of applying the negative voltage to node 93 and the positive voltage to node 95 in the other position of the switch. In effect, the operation of switch 84 merely connects the “battery” or source 82 to nodes 93 or 95 with mutually reversed polarities.
When the position of switch 84 of FIG. 1a is as illustrated, the positive terminal of source 82 is connected to node 93 and the negative terminal is connected to node 95, and in the other position of switch 84, the positive terminal of source 82 is connected to node 95 and the negative terminal is connected to node 93. In general, the conduction of the conductive path of a FET can be controlled with either a relatively positive or relatively negative voltage on the gate electrode, depending upon the design and doping of the channel, which is to say that it can operate in either an “enhancement” or “depletion” mode. A junction FET must be operated with the gate junction reverse-biased to maintain the high gate impedance. Forward bias of the gate junction in a junction FET at least lowers the gate impedance and decreases the voltage between the gate electrode and the conductive channel to one semiconductor junction offset voltage, generally referred to as Vg.
FIG. 1e is a simplified representation of those portions of the arrangement of FIG. 1a which are relevant to an analysis of the biasing of the FETs therein. Elements of FIG. 1e corresponding to those of FIG. 1a are designated by like reference numerals. In FIG. 1e, there is a direct-current conduction path extending from node 93 to node 95. The path includes, in order beginning from node 93, the resistance 92, the gate resistance or impedance of transistor 32, the resistance of the conductive path extending through node 24, the gate resistance or impedance of transistor 42, and the resistance of resistor 94. In this path, the resistance of the conductors extending through node 24 are very low. The resistances of resistors 92 and 94 are large, but do not control current flow in the gate circuit, because the gate resistance of at least one or the other of the FETs 32 or 34 is very high, and establishes the bias current flow from node 93 to node 95 regardless of the presence of resistances 92 and 95. Both FETs 32 and 42 will exhibit very large impedances, regardless of the polarization of the gate bias voltage. In the case of JFETs, only that one of the gate-to-conductive paths which is reverse biased will have a very high resistance, while the other gate will be forward-biased and have a very low resistance. The gate-to-drain or gate-to-path resistances are so great that the presence of gate resistances 93 or 95 make no difference to the gate current or the gate-to-drain voltage. Thus, the gate resistances such as 93 and 95 may be ignored for purposes of analysis.
In one case, the two high resistances may be connected in series, as represented by gate-to-drain resistances Rgd32 and Rgd42 in FIG. 1f. In such a series connection, the voltage drops across the gate-to-conductive-paths of the two FETs will be inversely related to their resistances. If they have the same gate resistances, the applied bias voltage will be divided equally between the two gate-to-drain resistances of the transistors, so that the voltage at node 24 of FIG. 1f will be ½ of the total voltage across control voltage terminals 93 and 95. If the gate-to-drain resistances Rgd32 and Rgd42 happen to be dissimilar, the bias voltage distribution across the two resistances will be unequal, and the voltage at node 24 will not be ½ the applied voltage, but some other ratio.
In the case of JFETs, one of the two FETs which is reverse biased will have a large resistance or impedance, and the other will have less than one volt of bias. This is illustrated in FIG. 1g, in which the series connection includes Rgd32, representing the large impedance of the reverse-biased semiconductor junction of FET 32, while the forward-biased gate-to-drain junction of FET 42 is represented by a diode symbol designated Vgd. Thus, in the case of JFETs the total bias voltage available at terminal 93, minus one Vgd, will appear across the reverse-biased gate-to-drain junction of that FETs which has a reverse-biased gate junction.
In the arrangement of FIG. 1a, the bias applied to the pair of FETs 32 and 42 is such as to render the controllable conductive path of one of the transistors conductive, and the other nonconductive. That one of the controllable paths 32p, 42p which is rendered conductive by application of appropriate gate bias becomes conductive, and responsive to the applied RF signal, while the other one of the controllable paths is rendered nonconductive, and nominally nonresponsive to the applied RF. The one controllable conductive path which is controlled to conduction may be termed ON, and the one which is controlled to nonconduction may be termed OFF. In use, the ON transistor conducts the RF signal between its individual port and the common port, and the OFF transistor provides little, and ideally no conduction, between its individual port and the common port. Thus, if RF signal is applied from source 12 to node 23, and transistor 32 is ON and transistor 42 is OFF, RF signal will be coupled to load resistor 20 at port 52 with little loss (so long as the resistance of the conductive path is small compared with the source resistance 16 and the load resistance 20 or 22). The path from node 23 to load resistor 22 at individual port or node 62 will be quite lossy, because transistor 42 is OFF, meaning that its conductive channel has a large resistance. In this state, the SPDT switch 10 may be said to be in a state that couples the signal preferentially to individual port or node 52, and not to port or node 62. Similarly, if RF signal is applied from source 12 to node 23, transistor 42 is ON and transistor 32 is OFF, RF signal will be coupled to load resistor 22 at port 62 with little loss, while the path from node 23 to load resistor 20 at individual port or node 52 will be quite lossy. In this state, the SPDT switch 10 may be said to be in a state that couples the signal preferentially to individual port or node 62, and not to port or node 52. It should be understood that the switch 10 can operate for RF conduction in the opposite direction, namely from individual port or node 52 to common port or node 23 (in one state of switch 10) or from individual port or node 62 to common node 23 (in the other state of switch 10).
It will be clear that during operation of RF switch 10 of FIG. 1a, there is a significant bias-related voltage at junction 24, and this bias voltage will, in general, be coupled through the path 32p, 42p of that one of the FET transistors 32, 42 which happens to be rendered conductive to the source terminal 32s, 42s of that FET. Capacitors 50 and 60 prevent application to the load resistances 20, 22 of this component of the direct bias voltage. This decoupling prevents changes in the bias applied to the RF switch 10 which might be attributable to the presence or absence of a load resistor at the independent, individual or separate ports of the switch, or to the use of load resistances which are of other than the design value.
FIG. 2 is a simplified diagram in block and schematic form of a SPDT RF switch 210, which is generally similar to switch 10 of FIG. 1a. In FIG. 2, each FET arrangement 30, 40 of FIG. 1a includes plural FETs arranged with their controlled current conducting paths in cascade. More particularly, in FIG. 2, FET arrangement 30 includes FETs 321, 322, and 323. The drain 323d of FET 323 is connected to the source 322s of transistor 322, and the drain 322d of transistor 322 is connected to the source 321s of transistor 321. Thus, the conductive paths of the three transistors 321, 322, and 323 are connected in series. In effect, the three transistors 32i, 322, and 323 have been “combined” to form a composite transistor corresponding to transistor arrangement 30, having as a source the source 323s of transistor 323, as a drain the drain 321d of transistor 321, and having a plurality of gates, namely gates 321g, 322g, and 323g spaced along the composite controlled conductive path. As illustrated in FIG. 2, the gates 321g, 322g, and 323g are connected in common to bias node 93 by way of individual resistors 921, 922, and 923, for common biasing of the gates to the composite conductive path. Similarly, FET arrangement 40 includes FETs 421, 422, and 423. The drain 423g of FET 423 is connected to the source 422s of transistor 422, and the drain 422d of transistor 422 is connected to the source 421s of transistor 421. Thus, the conductive paths of the three transistors 421, 422, and 423 are connected in series. In effect, the three transistors 421, 422, and 423 have been “combined” to form a composite transistor corresponding to transistor arrangement 40, having as a source the source 423s of transistor 423, as a drain the drain 421d of transistor 421, and having a plurality of gates, namely gates 421g, 422g, and 423g spaced along the composite controlled conductive path.
As illustrated in FIG. 2, the gates 421g, 422g, and 423g are connected in common to bias node 95 by way of individual resistors 941, 942, and 943, for common biasing of the gates to the composite conductive path. The multitransistor control arrangement of FIG. 2 by comparison with the single-transistor control of FIG. 1a provides the advantage of greater isolation between common port 23 and that individual port associated with the OFF path. It has the disadvantage that the loss in the ON path is greater than in the arrangement of FIG. 1a. In general, the use of a single transistor for each side of the RF switch has advantages and disadvantages relative to the use of plural cascaded or series transistors, but the basic principles of operation of such a switch are not dependent upon the number of cascaded transistors on each side.
Improved RF switch arrangements are desired.